The invention relates to a semiconductor memory element, a semiconductor memory element arrangement, a method for fabricating a semiconductor memory element and a method for operating a semiconductor memory element.
Some essential parameters of a semiconductor memory element are the retention time for which the memory content stored in the semiconductor memory element is preserved, the write time required for programming in the memory content, and the write voltages required for programming in the memory content.
A known semiconductor memory element is the DRAM memory element (DRAM=Dynamic Random Access Memory) which, although having relatively fast write times of a few nanoseconds, has only short retention times on account of unavoidable leakage currents, so that the RAM memory element has to be recharged at regular time intervals of about 100 ms.
By contrast, although the so-called EEPROM memory element (EEPROM=Electrically Erasable Programmable Read Only memory) enables relatively long retention times of a number of years, the write times required for programming in the memory content are significantly longer than in the case of the RAM memory element.
There is therefore a need for semiconductor memory elements in which fast write times (of about 10 nanoseconds) are combined with long retention times (of more than one year) and low write voltages.
K. K. Likharev, “Layered tunnel barriers for non-volatile memory devices”, Applied Physics Letters Vol. 73, pages 2137–2139 has proposed a so-called “crested barrier” memory element, in which a floating gate is charged or discharged via a serial arrangement of (typically three) tunnel barriers, the tunnel barriers having a profiled (=“crested”) form. In this case, the tunnel barriers are not formed in the customary manner in the form of a square-wave potential with a constant height of the potential barrier, but rather are profiled by means of “peaks”.
Since, compared with a conventional tunnel barrier, such a “profiled” tunnel barrier has a greater charge transmission and a greater sensitivity for the voltage present, relatively fast write times can be achieved theoretically in any case with such a “crested barrier” semiconductor memory element. However, the write voltages required for writing are relatively large, i.e. approximately greater than 10 V.
K. Nakazato et al., “PLED—Planar Localized Electron Devices”, IEDM pages 179–182 has disclosed a proposal for a so-called PLED memory element (PLED=Planar Localized Electron Device). In this case data is written or erased by fast charging or discharging of a floating gate via a multiple tunnel barrier (MTJ=Multiple Tunnel Junction), the transmission of the multiple tunnel barrier being controlled by means of a side gate electrode. For reading data, depending on the conductivity state of the channel running below the floating gate between a source terminal and a drain terminal, a current flow is detected in the channel (corresponding to a “1” bit) or is not detected (corresponding to a “0” bit). In the case of the PLED memory element, it is possible to achieve short write times (similar to those of a RAM memory element) and long retention times (similar to those of an EEPROM memory element). Moreover, the required write voltages are significantly lower than in the case of the “crested barrier” memory element mentioned above.
However, since a further terminal is required for the side gate electrode for controlling the transmission of the tunnel barrier in addition to the source, drain and data terminals, the PLED memory element is a 4-terminal arrangement. On account of this 4-terminal arrangement, the PLED memory element has relatively large dimensions and, consequently, is not ideal for ULSI applications (ULSI=Ultra Large Scale Integration).